1. Field of the Invention
The present invention generally relates to a semiconductor memory device, and particularly to a nonvolatile semiconductor memory device, in which memory cells include resistance elements having resistance values varying in accordance with storage data. More particularly, the invention relates to a structure for reducing a current consumption of a semiconductor device, particularly a nonvolatile semiconductor memory device.
2. Description of the Background Art
Such a memory device is known that a variable resistance element is utilized in a memory cell, and data is nonvolatilely stored by a resistance value of this variable resistance element. A phase change memory and a Magnetic Random Access Memory (MRAM) are known as the memory of such type.
In the phase change memory, a material such as polycrystalline silicon is set to an amorphous state or a crystalline state in accordance with data to be stored. Since the amorphous state and the crystalline state provide different resistance values, binary data can be stored.
The MRAM is a general name of solid state memories, which utilize a magnetization direction of a ferromagnet for data storage. In MRAM, the magnetization direction of the ferromagnetic substance forming a memory cell is set parallel and anti-parallel to a certain reference direction in accordance with data “1” and “0”, respectively. The MRAMs include a GMR (Giant Magneto-Resistance) element utilizing a GMR effect for reading storage information of the memory cell, and a TMR (Tunneling Magneto-Resistance) element utilizing a tunneling magneto-resistance effect for reading the storage data.
GMR element has a resistance changing rate ranging from 6 to 8%, and has a disadvantage that a sense current of the order of 10 mA is required in a data read operation. In contrast, the TMR element is formed of three layer films of ferromagnetic, insulating and ferromagnetic layers, and a current flows by tunneling through the insulating layer. This tunneling resistance value changes in proportion to a cosine of a relative angle between the ferromagnetic layers on the opposite sides relative to the insulating film. TMR element has a feature that the resistance changing rate is 25% or higher, and a sense current of as small as 10 μA can provide a sufficiently large read signal.
FIG. 20 schematically shows a sectional structure of a memory cell. In FIG. 20, the memory cell includes a data storing portion S. Data storing portion S is arranged corresponding to a crossing between a write word line WWL and a write bit line WBL, and includes ferromagnetic layers 901 and 903, a dielectric layer 902 arranged between ferromagnetic layers 901 and 903, and an anti-ferromagnetic layer 904 placed between ferromagnetic layer 903 and write bit line WBL. Ferromagnetic layer 903 and anti-ferromagnetic layer 904 form a fixed layer having a fixed magnetization direction. The magnetization direction of ferromagnetic layer 901 is set by a word line current Iwl flowing through write word line WWL and a bit line current Ibl flowing through write bit line WBL, so that the data is stored.
When word line current Iwl flows, a magnetic field Hwl is induced rotating clockwise with respect to a flowing direction of current Iwl. When current Ibl flows through write bit line WBL, a magnetic field Hbl is induced rotating clockwise in a plane perpendicular to a flowing direction of bit line current Ibl. Write word line WWL and write bit line WBL are arranged perpendicular to each other, and the magnetic fields Hwl and Hbl are likewise perpendicular to each other. A composite magnetic field formed of these magnetic fields Hwl and Hbl determines the magnetization direction of ferromagnetic layer 901, and data is stored. When ferromagnetic layer 901 serving as a record layer and anti-ferromagnetic layer 904 of the fixed layer have the same magnetization direction, the data storing portion S has a small electric resistance value. When ferromagnetic layers 901 and 903 have anti-parallel magnetization directions or opposite magnetization directions, the data storing portion S has a high electric resistance.
In a data reading operation, a tunnel current flows through dielectric layer 902 in the data storing portion S, and data is read by detecting an amount of this current. The current flowing through a memory cell is a tunnel current flowing through thin dielectric layer 902. A “magnetic-tunneling junction” is formed in the memory cell and the memory cell is also referred to as a MTJ memory cell.
In using the GMR element, a nonmagnetic electric conductor is used in place of the dielectric layer.
FIG. 21 schematically shows a general sectional structure of a memory cell.
In the memory cell structure shown in FIG. 21, the storing portion S is arranged between write bit line WBL and a cell node CN. Cell node CN is formed of an electrically conductive layer, and is electrically connected to an N-type impurity region IMPb formed at a surface of a P-type substrate region SUB. An N-type impurity region IMPa is formed being spaced from impurity region IMPb at the surface of substrate region SUB. A read word line RWL is formed above a surface of the substrate region between these impurity regions IMPa and IMPb. Impurity region IMPa is coupled to read bit line RBL via a contact. Write word line WWL is arranged between read bit line RBL and cell node CN.
In a data read operation, the magnetization direction of the storing portion S is determined by the composite magnetic field of magnetic fields that are induced by currents flowing through write bit line WBL and write word line WWL. Therefore, the magnetization direction of the record layer with respect to the fixed layer is determined by setting the direction of the current flowing through the write bit line in accordance with the storage data, and data is written.
In the data read operation, read word line RWL is set to a selected state to form a channel at the surface of substrate region SUB for electrically coupling impurity regions IMPa and IMPb. A current flows from write bit line WBL to read bit line RBL, and the data stored in the storing portion S is detected in accordance with an amount of the current.
FIG. 22 shows an electrically equivalent circuit of a memory cell MC. In FIG. 22, memory cell MC includes a variable resistance element 912 and an N-channel MOS transistor 910 connected in series between write and read bit lines WBL and RBL. Variable resistance element 912 has an end electrically connected to write bit line WBL, and is also electro-magnetically coupled to write word line WWL. N-channel MOS transistor (access transistor) 910 has an conduction terminal electrically connected to the other end of variable resistance element 912, the other conduction terminal electrically coupled to read bit line RBL, and a control gate electrically connected to read word line RWL.
In the data write operation, currents flow through write word line WWL and write bit line WBL to induce the magnetic fields, which in turn determine a magnetic polarization state of variable resistance element 912, and the resistance value of the variable resistance element is determined depending on the magnetic polarization state. In the data read operation, access transistor 910 is turned on, and the data is sensed in accordance with the magnitude of the currents flowing through write and read bit lines WBL and RBL.
In the structure having the variable resistance element (TMR element) and the access transistor connected in series, the current flowing through access transistor 910 is needed to detect in the data read operation. Therefore, if characteristics of the access transistors vary, read current differ among the access transistors, and noises caused by these variations cannot be neglected. For example, in the MOS transistor (insulated gate field effect transistor), an electric field drop between the source and drain amounts to 100 mV or more in 0.25 μm rule. Accordingly, if variations of 10% are present in the characteristics of the access transistors, noises of 10 mV or more occur. With noises caused by peripheral circuitry taken into account, the noise level reaches 10 mV or higher. Therefore, a sufficient signal-to-noise ratio cannot be achieved in the TMR element, for which a sense current of 10 μA can provide a memory cell read voltage of 25 mV.
For improving the signal-to-noise ratio, such an approach is widely used that an output voltage of a selected memory cell is compared with a reference voltage, and the differential voltage is amplified. In this differential amplification using the reference voltage, a dummy cell is generally used. The dummy cell having the same characteristics as the memory cell is used for the purpose of removing noises occurring on a data line of the selected memory cell and canceling an offset in memory cell output voltage due to variations in characteristics of the access transistors of the memory cells.
However, in the circuit for generating the reference voltage, the selected memory cell and the dummy cell are connected to different access transistors. Therefore, it is difficult to remove completely the offset in output voltage of the memory cell, which is caused by variations in characteristics of the access transistors.
The difference in sense current between H- and L-level data is on the order of microampere (μA). In the case of utilizing the reference voltage, the reference voltage is required to have a magnitude intermediate between the magnitudes of the memory cell currents or memory cell voltages in reading H- and L-data. A difference between the reference voltage and memory cell voltage or between the reference current and memory cell current is further reduced, so that a malfunction may occur due to variations in transmission characteristics between a path transferring data of the selected memory cell and a path transferring data of the dummy cell.
A tunnel film (a dielectric film of the TMR element) of the memory cell is an insulating film causing a tunnel current to flow, and has a resistance value depending on the film thickness. Accordingly, if variation is present in film thickness of the tunnel film, this increases difference in resistance value of the tunneling film between the selected memory cell and the dummy cell, so that differential input voltages to the differential amplifier may become insufficient or inverted. Therefore, the memory cell data cannot possibly be accurately detected.
FIG. 23 shows an example of a structure of a write driver for driving write bit line WBL. In accordance with the write data, one of the write drivers arranged on the opposite sides of write bit line WBL is activated. More specifically, the word line driver arranged for write word line WWL supplies a current to the selected write word line in a fixed direction regardless of the write data. In write bit line WBL, a flowing direction of the current is determined depending on the write data. FIG. 23 shows a write driver 950 arranged on one side of write bit line WBL.
Write driver 950 includes a P-channel MOS transistor 952 for coupling write bit line WBL to a power supply node when made conductive, and an N-channel MOS transistor 954 for electrically coupling write bit line WBL to a ground node when made conductive.
During a standby state, write driver 950 is supplied with a signal at H level (a level of power supply voltage VCC). In this state, write bit line WBL is maintained at the ground voltage level. In MOS transistor 952, however, a subthreshold current Il flows even if their gate and source are at the same level of power supply voltage VCC. This subthreshold current Il is discharged to the ground node via MOS transistor 954 in the conductive state.
Even if read word line RWL is at the ground voltage level during the standby, a subthreshold current likewise flows via access transistor 910 in memory cell MC. Accordingly, leakage current Ilb flowing from bit line write driver 950 to write bit line WBL further flows through variable resistance element (TMR element) 912 and access transistor 910 to read bit line RBL kept at the ground voltage level. Write bit line WBL is arranged corresponding to each column of memory cells MC, and the write drivers on one side are equal in number to the memory cell columns, precisely two times the number of the memory cell columns. Therefore, a sum of leakage currents Il (Ila and Ilb) during the standby takes an innegligible value.
Drivers similar to bit line write driver 950 are provided for write word line WWL and for read word line RWL, so that leakage currents flow due to subthreshold currents in MOS transistors provided therein during the standby. Accordingly, the leakage currents in this drive circuit group increase the current consumption during the standby, so that a specification requirement of an ultra low standby current, which is required for application such as portable equipment, cannot be satisfied, and the application range is restricted.
For reducing the subthreshold current, it may be considered to increase an absolute value of the threshold voltage. In this case, however, the responsivility of the MOS transistor is deteriorated, and a drive current also decreases, if the transistor size is unchanged. Accordingly, if the absolute value of the threshold voltage is made great, it is impossible to reduce the transistor sizes for a faster operation, and thus the device shrinking is impeded.